A methodology for modeling the effects of systematic within-die interconnect and device variation on circuit performance,” DAC 2000

Abstract: We present a methodology to study the impact of spatial pattem dependent variation on circuit performance and implement the technique in a CAD framework. We investigate the effects of interconnect CMP and poly CD device variation on inter-connect delay and clock skew in both aluminum and copper inter-connect technology. Our results indicate that interconnect CMP variation strongly affects interconnect delay, while poly CD varia-tion has a large impact on clock skew in a 1 GHz design. Given this circuit impact, CAD tools in the future must account for such systematic within-die variations.